1. Field of the Invention
The present invention relates to a clock regeneration circuit for generating a clock signal that is synchronized to an input signal.
Priority is claimed on Japanese Patent Application No. 2008-044414, filed Feb. 26, 2008, and the content of which is incorporated herein by reference.
2. Description of Related Art
In radio communication, clock regeneration circuits are used to generate clock signals that are used in order to regenerate data from received signals that contain jitter. In a clock regeneration circuit, it is necessary to synchronize the received signal and the clock signal accurately. For this purpose, Japanese Unexamined Patent Application, First Publication No. H10-215289 has disclosed a method of generating a histogram indicating the number of times of detection of each position of signal transition points, from a received signal, and determining a representative phase based on the maximum value of the histogram generated, in order to optimize the phase of the clock signal.